The present disclosure relates to a semiconductor device, and, more particularly, to a wiring layout and structure within a memory cell structure of a semiconductor memory device.
An exemplary wiring layout and structure of a memory cell of a conventional semiconductor memory device is illustrated in FIGS. 1A, 1B, and 2. A semiconductor memory device includes a memory cell array portion (MCA) 100 having a plurality of mutually parallel word lines (WL) 102, a plurality of bit lines (BL) 104 intersecting the plurality of word lines 102, and a plurality of memory cells (MC) 106 formed at intersections of the word lines 102 and the bit lines 104, and a peripheral portion where peripheral circuits such as a sense amplifier or a decoder are formed.
In the memory cell array portion 100 where the memory cells 106 are formed, the element integration level is high, and a fine pattern is formed. In the peripheral portion where the peripheral circuits are formed, the element integration level is lower than that of the memory cell array portion 100, and a coarse pattern is formed. In general, the spaces between the wiring and elements are wide.
During a photolithography process, in the vicinity of the boundary of the fine pattern and the coarse pattern, the resist application becomes uneven, or the amount of exposure becomes uneven due to diffracted light. Moreover, a loading effect may occur due to a different etching rate during an etching process, depending on a difference in density of a chip pattern on a semiconductor wafer: the etching rate is high in the fine pattern while it is low in the coarse pattern. For these reasons, a problem may arise in that the dimension or shape of the word lines 102, the bit lines 104, or the contact plugs (hereinafter, referred to simply as contacts) differs between the interior (high-density pattern) and near the exterior (low-density pattern) of the memory cell array portion 100. As used herein, density generally refers to the number of contact plugs per unit area. In other words, there are more contact plugs per unit area in a higher density area than in a lower density area.
To solve such a problem, in a conventional semiconductor memory device, dummy word lines 108, dummy bit lines, or dummy contacts 110 are arranged near the exterior 101 of the memory cell array portion 100. With such an arrangement, the dimensions or shapes of the word lines 102, the bit lines 104, or the contacts (which are actually used) near the exterior 101 of the memory cell array portion 100 are made the same as these in the interior of the memory cell array portion 100.
FIGS. 1A and 1B illustrate an example in which both the dummy word lines 108 and the dummy contacts 110 are arranged near the exterior 101 of the memory cell array portion 100. FIG. 2 illustrates an example in which only the dummy word lines 108 are arranged near the exterior 101 of the memory cell array portion 100. See, for example, Japanese Patent No. 3575988, which is incorporated by reference.
The semiconductor memory device having the conventional structure described above with reference to FIGS. 1A, 1B, and 2 has several problems. In the example of FIGS. 1A and 1B, uniform dimensions and shapes of the word lines 102 and the contacts 112 can be ensured up to the exterior 101 of the memory cell array portion 100. However, when the dummy contacts 110 are short-circuited with the dummy word lines 108, it may lead to a problem that the dummy word lines 108 and the bit lines 104 are also short-circuited. Such a problem is particularly considerable when a self-aligned contact is used for forming of the contacts. In the self-aligned contact, since a mask insulating film serving as an etching stop is formed on a gate electrode, it is possible to form a contact that is not electrically connected to the gate electrode even when it is vertically misaligned, so that the distance between gates can be reduced and, thus, a high integration level can be realized.
As a countermeasure, in the example of FIG. 2 illustrating a technique disclosed in Japanese Patent No. 3575988, only the dummy word lines 108 are arranged near the exterior 101 of the MCA 100, while the dummy contacts 1 10 are not. With such an arrangement, the dummy contacts 110 are not short-circuited with the dummy word lines 108. However, since the dummy contacts 110 are not present, in a case where it is difficult to ensure a uniform dimension or shape of the contacts 112 in the vicinity of the boundary of the fine pattern and the coarse pattern, the contacts 112 might be short-circuited with the word lines 102, and, thus, the word lines 102 and the bit lines 104 might also be short-circuited.